1. Field of the Invention
This invention relates to a sense amplifier for receiving signals of data read out from a semiconductor memory cell array and operating as a component of a read circuit for reading and transmitting data stored in a semiconductor memory such as an EPROM, EEPROM or mask ROM.
2. Description of the Related Art
Jpn. Pat. Appln. DOKAI Publication No. 58-125282 discloses a read circuit for a semiconductor memory having a configuration as illustrated in FIG. 12 of the accompanying drawings. A semiconductor memory of the type under consideration is normally provided with a memory cell array 11 comprising a number of memory cells Q5ll-Q5mn arranged in a matrix of m rows and n columns, of which a row can be selected by a corresponding signal of row select signals SRl-SRm transmitted from a row decoder 12. Output of each of the rows of the memory cell array 11 are collectively sent to column select transistors Q4l-Q4n, one of which is then selected by a corresponding signal of column section signals SCl-SCn transmitted from a column decoder 13. The output of a specific memory cell may then be selectively read out by the row decoder 12 and the column decoder 13. The signal representing the data read out from a selected one of the memory cells of the memory cell array 11 is then fed to a sense amplifier 14. The sense amplifier 14 comprises a load transistor Q1 constituted by a P-channel MOS transistor and a memory cell output detection circuit 15, which in turn is constituted by a read/write switching transistor Q2 for receiving read/write switching signal R. The output signal from the memory cell array 11 is fed to the load transistor Q1 by way of the read/write switching transistor Q2.
Output a from the output terminal of the memory cell output detection circuit 15 is then fed to both the non-inversion side input terminal of a differential amplifier 16a, and the inversion side input terminal of a differential amplifier 16b. These differential amplifiers 16a and 16b individually compare the output they receive with a reference voltage vref. Then, the properly phased output c and the inversely phased output c from the differential amplifiers 16a and 16b are compared with each other by a differential amplifier 17. Their phases are inverted by an inverter 18 before they are taken out through an output terminal O as output of the sense amplifier.
Thus, a total of three differential amplifiers need to be installed in a sense amplifier having a configuration as described above, inevitably making the size of the overall circuit rather large. Additionally, since the differential amplifiers 16a and 16b are connected to respective signal transmission paths between the output terminal of the memory cell output detection circuit 15 and the differential amplifier 17 to compare their output, the delay time in the response of the differential amplifiers 16a and 16b is added to the time required for a specific data to be read out of the memory cell array. Consequently, the overall time required for a data reading operation is increased.